What are the requirements for FPGA power supply design
As a complex integrated circuit, the design of the power supply for the FPGA system has higher requirements than general electronic systems, and needs to have the characteristics of high precision, high density, controllability, high efficiency and miniaturization. This article introduces the different characteristics of FPGA power supply, and at the same time, through examples, you can have a deeper understanding of the meaning of each characteristic, as well as FPGA specification constraints and their impact on power supply design, so that you can quickly complete the power supply design of FPGA systems.
FPGAs are among the most complex integrated circuits available today. They use advanced transistor technology and chip architecture to achieve high-performance, small-scale high-end products, and the power supply for powering FPGA systems is more demanding than general electronic systems.
With the popularity of FPGA system applications in the market, the demand for its power supply solutions is also growing. In addition to meeting basic requirements, FPGA power systems also need to have high precision, high density, controllability, high efficiency and small size. characteristics, etc.
Voltage accuracy
The core supply voltage is one of the most critical elements in balancing FPGA power and performance. The acceptable voltage range is generally listed in the specification, but this range is not a complete description. For FPGAs, the power supply voltage needs to be weighed and optimized while meeting the circuit operation requirements.
Figure 1 below uses Intel’s Arria 10 FPGA core voltage requirements as an example, which also represents the voltage requirements of other FPGA cores. Generally, the tolerance range rated voltage is displayed, for example, the Arria 10 FPGA is ±0.03V, and the FPGA will operate well within this voltage window, but the actual situation is much more complicated than the picture shows.
In fact, FPGAs can operate at different voltages, depending on their particular manufacturing tolerances and the specific logic design employed. Even with the same voltage requirements, the static voltage required by one FPGA may be different from that of another FPGA, so the power supply design must take into account the dynamic and static changes of the corresponding FPGA and adjust it by itself
Dynamic and static power
When designing an appropriate FPGA power scheme, the goal is to produce the right level of performance to operate programming functions and reduce unnecessary power consumption. From a semiconductor physics perspective, both dynamic and static power increase significantly with core VDD, so our goal is to have the FPGA run properly with enough voltage to meet its timing requirements—because the excess power consumption is not only It doesn’t do anything to improve performance, instead it causes transistor leakage current to heat up, consuming more power unnecessarily. For these reasons, it is imperative to optimize the design and voltage at the operating point.
This optimization process requires a very precise power supply to be successful. If the core voltage is lower than required, the FPGA may fail due to timing errors. If the core voltage drifts beyond the maximum specification, the FPGA may be damaged, or hold time faults may be created in the logic. Therefore, the power supply tolerance range must be considered to prevent all these conditions, and only the commanded voltage is guaranteed to remain within the specification limits.
The problem is that most power regulators are not accurate enough. The regulated voltage can be anywhere within tolerance around the commanded voltage, and it can drift with load conditions, temperature, and aging. A ±2% tolerance power supply means it can output any value within a 4% voltage range. To compensate for the possibility of voltage being 2% too low, the commanded voltage must be 2% higher than required to meet timing. If the voltage drifts past the regulator to 2% above the commanded voltage, it will run 4% above the minimum voltage required for that operating point. This still meets the voltage requirements required by the specified FPGA, but wastes a lot of power.
The solution to this problem is to choose a power regulator that can operate with tighter voltage tolerances. Using a regulator with ±0.5% tolerance allows operation at the desired operating frequency, closer to the minimum required specification, and guaranteed to be less than 1% from the desired voltage. In this way, the FPGA can work normally with minimal power consumption.
high power demand
Devices in an FPGA system often require different regulation voltages, such as a voltage core voltage processor, which requires a voltage of 0.8V, 1.0V, 1.2V, 1.5V, or 1.8V, etc. Although it is a low-voltage supply, its dense transistor structure and long-term high-speed operation may require a power supply scheme of 10A or more.
Specific processor requirements often dictate other power requirements, such as load transient recovery, standby mode, etc., which require a Point-of-Load (PoL) regulated power supply designed for the core voltage.
A PoL regulated power supply is a high-performance regulator where each Vout voltage rail is independent of its respective load setting. This helps address the high transient current requirements and low noise requirements of high performance semiconductor devices such as FPGAs. For example, ADI’s LTM4678 series includes two sets of high-density power supply outputs, 1V@25A and 1.8V@25V, respectively.
controllability requirements
An FPGA contains a large and complex arrangement of transistors, and a chip contains hundreds of millions of transistors, which are divided into core segments, module segments, and partitions that can be designed and independently managed. These particular arrangements are that there are many different power domains, in addition to voltage, current, ripple, and noise, but also the sequence order during startup, shutdown, and fault conditions, so a controllable FPGA power supply needs to properly manage the output sequence and its power
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